In the three-dimensional (3-D) packaging of focal plane signal processing electronics, silicon dies are stacked together vertically and bonded to form a module assembly. This necessitates the routing of conductors from the face of the die to the edge of the die for placement of inter-connects to the next assembly. In such a routing method, there arises a problem of electrical isolation of these conductors from the underlying silicon, especially when the silicon is highly doped and remains conductive at the operating temperature of the module.